# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do proctest_tf.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module register16bitwrite
# 
# Top level modules:
# 	register16bitwrite
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module register16bit
# 
# Top level modules:
# 	register16bit
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module fulladd1
# 
# Top level modules:
# 	fulladd1
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module M2_1E_MXILINX_aluone
# -- Compiling module M4_1E_MXILINX_aluone
# -- Compiling module M2_1_MXILINX_aluone
# -- Compiling module aluone
# 
# Top level modules:
# 	aluone
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module NOR16_MXILINX_alu16bit
# -- Compiling module alu16bit
# 
# Top level modules:
# 	alu16bit
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module add16bit
# 
# Top level modules:
# 	add16bit
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module M2_1_MXILINX_comparer
# -- Compiling module INV16_MXILINX_comparer
# -- Compiling module comparer
# 
# Top level modules:
# 	comparer
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module busconcat
# 
# Top level modules:
# 	busconcat
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module bus_mux1
# 
# Top level modules:
# 	bus_mux1
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module decode1
# 
# Top level modules:
# 	decode1
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module busthing
# 
# Top level modules:
# 	busthing
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module concat8x8
# 
# Top level modules:
# 	concat8x8
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module mux4
# 
# Top level modules:
# 	mux4
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module mux4x16
# 
# Top level modules:
# 	mux4x16
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module regwclock
# 
# Top level modules:
# 	regwclock
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module regs
# 
# Top level modules:
# 	regs
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module finalregtest
# 
# Top level modules:
# 	finalregtest
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module addr_select
# 
# Top level modules:
# 	addr_select
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module distromv
# 
# Top level modules:
# 	distromv
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module xcontrol
# 
# Top level modules:
# 	xcontrol
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module dirtybusmux8
# 
# Top level modules:
# 	dirtybusmux8
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module dirtybusmux2
# 
# Top level modules:
# 	dirtybusmux2
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module busthingy
# 
# Top level modules:
# 	busthingy
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module dirtybusmux3_4bit
# 
# Top level modules:
# 	dirtybusmux3_4bit
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module dirtybusmux3_16bit
# 
# Top level modules:
# 	dirtybusmux3_16bit
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module dirtybusmux2_4bit
# 
# Top level modules:
# 	dirtybusmux2_4bit
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module dirtybusmux5_16bit
# 
# Top level modules:
# 	dirtybusmux5_16bit
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module M2_1_MXILINX_shifter
# -- Compiling module M2_1E_MXILINX_shifter
# -- Compiling module M16_1E_MXILINX_shifter
# -- Compiling module shifter
# 
# Top level modules:
# 	shifter
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module leftshifter
# 
# Top level modules:
# 	leftshifter
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module ByteRam
# 
# Top level modules:
# 	ByteRam
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module processor
# 
# Top level modules:
# 	processor
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module testbench
# 
# Top level modules:
# 	testbench
# testbench
# vsim -L xilinxcorelib_ver -L unisims_ver -L simprims_ver -lib work -t 1ps testbench glbl 
# ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.# Loading work.testbench
# Loading work.processor
# Loading work.alu16bit
# Loading work.aluone
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.AND2
# Loading work.fulladd1
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.OR3
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.XOR3
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.GND
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.INV
# Loading work.M2_1_MXILINX_aluone
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.AND2B1
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.OR2
# Loading work.M4_1E_MXILINX_aluone
# Loading work.M2_1E_MXILINX_aluone
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.AND3
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.AND3B1
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.MUXF5
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.VCC
# Loading work.NOR16_MXILINX_alu16bit
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.FMAP
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.MUXCY
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.MUXCY_L
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.NOR4
# Loading work.busconcat
# Loading work.busthing
# Loading work.busthingy
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.BUF
# Loading work.ByteRam
# ** Warning: (vsim-3009) [TSCALE] - Module 'ByteRam' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_230
# Loading work.comparer
# Loading work.add16bit
# ** Warning: (vsim-3009) [TSCALE] - Module 'add16bit' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_20/adder16bit
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/xilinxcorelib_ver.C_ADDSUB_V6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/xilinxcorelib_ver.C_REG_FD_V6_0
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.AND3B2
# Loading work.INV16_MXILINX_comparer
# Loading work.M2_1_MXILINX_comparer
# Loading work.dirtybusmux2
# ** Warning: (vsim-3009) [TSCALE] - Module 'dirtybusmux2' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_150
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/xilinxcorelib_ver.C_MUX_BUS_V6_0
# Loading work.dirtybusmux2_4bit
# ** Warning: (vsim-3009) [TSCALE] - Module 'dirtybusmux2_4bit' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_159
# Loading work.dirtybusmux3_16bit
# ** Warning: (vsim-3009) [TSCALE] - Module 'dirtybusmux3_16bit' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_158
# Loading work.dirtybusmux3_4bit
# ** Warning: (vsim-3009) [TSCALE] - Module 'dirtybusmux3_4bit' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_157
# Loading work.dirtybusmux5_16bit
# ** Warning: (vsim-3009) [TSCALE] - Module 'dirtybusmux5_16bit' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_203
# Loading work.dirtybusmux8
# ** Warning: (vsim-3009) [TSCALE] - Module 'dirtybusmux8' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_146
# Loading work.finalregtest
# Loading work.regs
# Loading work.bus_mux1
# ** Warning: (vsim-3009) [TSCALE] - Module 'bus_mux1' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_138/XLXI_1/XLXI_33
# Loading work.concat8x8
# Loading work.decode1
# ** Warning: (vsim-3009) [TSCALE] - Module 'decode1' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_138/XLXI_1/XLXI_54
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/xilinxcorelib_ver.C_DECODE_BINARY_V6_0
# Loading work.mux4x16
# Loading work.mux4
# ** Warning: (vsim-3009) [TSCALE] - Module 'mux4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_138/XLXI_1/XLXI_114/XLXI_1
# Loading work.regwclock
# ** Warning: (vsim-3009) [TSCALE] - Module 'regwclock' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_138/XLXI_1/XLXI_136
# Loading work.leftshifter
# Loading work.shifter
# Loading work.M16_1E_MXILINX_shifter
# Loading work.M2_1_MXILINX_shifter
# Loading work.M2_1E_MXILINX_shifter
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.MUXF5_L
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/verilog/unisim_ver.MUXF6
# Loading work.register16bit
# ** Warning: (vsim-3009) [TSCALE] - Module 'register16bit' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/B
# Loading work.register16bitwrite
# ** Warning: (vsim-3009) [TSCALE] - Module 'register16bitwrite' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/PC
# Loading work.xcontrol
# Loading work.addr_select
# ** Warning: (vsim-3009) [TSCALE] - Module 'addr_select' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_154/XLXI_3
# Loading work.distromv
# ** Warning: (vsim-3009) [TSCALE] - Module 'distromv' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testbench/UUT/XLXI_154/XLXI_36
# Loading work.glbl
# WARNING: Design size of 19525 statements or 3 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# .wave
# ** Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use.
# File in use by: LocalMgr  Hostname: ERSSONKK-1  ProcessID: 3556
# ** Warning: (vsim-WLF-5001) Could not open log file vsim.wlf.  Using C:\DOCUME~1\erssonkk\LOCALS~1\Temp\wlft4.wlf instead.
# .structure
# .signals
# ** Warning: (vsim-PLI-3408) Too few data words read at line 298 of "main_prog_bin.txt". Expected 512, found 298.    : byteRAM.v(121)
#    Time: 0 ps  Iteration: 1  Instance: /testbench/UUT/XLXI_230
run -all
# Break key hit 
# Simulation stop requested
